A generalized MASH architecture in Fractional-N synthesizer

Sigma-Delta Modultation is playing a more and more important role in Fractional-N PLL synthesizer. MASH structure is prevailing in Fractional-N PLLs because of its intrinsic stability. 2(nd) and 3(rd) order MASH modulators have been reported in Fractional-N systems, but little about higher order Sigma-Delta modulators. In this article, a new optimized algorithm is developed, base on this general algorithm MASH modulator with arbitrary high order can be implemented with more flexibility and less hardware effort. This structure is very easy to be integrated into embedded systems, and also can be extended to be use in coding and oversample DAC/ADC systems. Both methematic analysis and simulation are presented.