MPEG-4 accelerator for PC based codec implementation

被引：0

作者：

Lim, YK ^{[1
]}

Kwak, J ^{[1
]}

Park, S ^{[1
]}

机构：

[1] Elect & Telecommun Res Inst, Video Commun Sect, Yusong Gu, Taejon 305350, South Korea

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In the MPEG-4 world, a scene is described as a composition of independent audiovisual objects that the user can access and manipulate. The MPEG-4 video being currently standardized will provide a toolbox containing tools and algorithms brining solutions enabling functionality. So it is very difficult to satisfy the various MPEG-4 video requirements using dedicated hardwares. In this paper we propose a flexible and high performance hardware architecture using DSP in conjunction with an MEMC (Motion Estimation and Motion Compensation) ASIC chip to implement MPEG-4 video codec. We developed the MEMC chip for an MPEG-2 MP@ML encoder. In order to see if it is possible to adopt the MEMC chip for the MPEG-4 accelerator, we simulated a modified MPEG-4 Video VM (Verification Model). The results of computer simulation showed that we can adopt the MEMC chip to implement MPEG4 video.

引用

页码：C182 / C185

页数：4