Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits

被引：16

作者：

Srivastava, A ^{[1
]}

机构：

[1] Louisiana State Univ, Dept Elect & Comp Engn, Baton Rouge, LA 70803 USA

来源：

MICROELECTRONICS RELIABILITY | 2000年 / 40卷 / 12期

关键词：

D O I：

10.1016/S0026-2714(00)00013-5

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Key building blocks - simple ternary inverter, positive ternary inverter and negative ternary inverter have been designed for operation at a low voltage - +/-1 V in 2 mum, n-well standard CMOS process and simulated in SPICE3 for use in the design of ternary logic circuits. The back-gate bias method has been used in conjunction with the width/channel (W/L) ratio of MOSFETs to generate the desired de voltage transfer characteristics and transition region adjustment around midway between high and low logic levels. (C) 2000 Elsevier Science Ltd. All rights reserved.

引用

页码：2107 / 2110

页数：4

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