An integrated CMOS RF synthesizer for 802.11a wireless LAN

A frequency synthesizer combining a relatively large tuning range (4.12-4.72 GHz) with a low noise sensitivity is presented. A stable fine-tuning loop is combined with an unstable coarse-tuning loop in parallel. As a result, a stable phase-locked loop (PLL) with a relatively wide tuning range and a moderate level of reference spurs is obtained. By adding a resistorless coarse-tuning loop, the tuning range was increased by a factor of four with no penalty in terms of phase noise, reference spurs, and settling speed. Also, the additional chip area and power consumption are negligible. The CMOS PLL circuit fabricated in a 0.25-mum technology is aimed at multiband WLAN transceivers.