Performance evaluation of adiabatic gates

In this paper, buffer and NAND-NOR adiabatic gates are compared to a gate designed with the traditional complementary metal-oxide-semiconductor (CMOS) approach. The comparison is carried out assuming both an assigned power supply and by setting its value in such a way as to minimize power consumption. General relationships, which are independent of process parameters, as well as being simple enough to be used in a pencil-and-paper evaluation, are calculated. The analysis is developed in detail for the fully adiabatic gates and extended to include partially adiabatic circuits such as 2N-2P and 2N-2N2P, The analytical results are validated by SPICE Simulations using 0.8-mum CMOS technology. The analysis shows that with the technology considered and a fan-out of three, the adiabatic buffer is advantageous at power clock rise times higher than 3 ns and 23 ns for the nonoptimized and the optimized design, respectively, assuming a 100-fF load capacitance. These rise times increase to 22 ns and 384 ns for the NAND-NOR gate. Moreover, all the minimum rise times increase linearly when the fan-out of the gate is increased.