Demonstration of Real Time pattern correction for high throughput maskless lithography

MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams[1]. In this way electron optical columns can be made with a throughput of 10 wafers per hour. The amount of data for each 26mm x 33mm field is 8 Tbyte. The data rate is approximately 3 Tbyte per second. In order to realize overlay the patterns for different fields on the wafer need to be slightly adjusted. Additionally it is beneficial for the electron optics design to be able to correct a number of tool parameters on the data. For this it is desirable to be able to correct the pattern data in real time. By implementing the correction algorithms on an FPGA test board it has been demonstrated that it is possible to perform the corrections on the exposed data real time. By using a pixel size of 3.5nm, a CDu and overlay contribution of smaller than 1nm 3s is obtained. A datapath for 10wph based on an FPGA implementation that stores the switching data uncompressed in DRAM fits in 4 racks of 2 meters high, with a footprint of 600mm x 700mm each. By replacing the FPGA by an ASIC implementation, and by using real time decompression, the footprint can be reduced in a later stage.