A graph-based framework for High-level test synthesis

被引：0

作者：

Bashari, Ali Pourghaffari ^{[1
]}

Pourmozafari, Saadat ^{[1
]}

机构：

[1] Amirkabir Univ Technol, Comp & IT Dept, Hafez Ave, Tehran, Iran

来源：

WORLD CONGRESS ON ENGINEERING 2007, VOLS 1 AND 2 | 2007年

关键词：

BIST; synthesis; testability; register allocation; (C)BILBO;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniques have changed their way from traditional DFT to modern SFT approach. In this paper, we present a novel flexible register allocation method for digital circuits, which is based on considering testability parameters as weights of register compatibility graph and weighted graph maximum clique algorithm in which during the synthesis, testability considerations impact on register allocation.

引用

页码：486 / +

页数：2

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