Design of a cell in embryonic systems with improved efficiency and fault-tolerance

This paper presents a new design of cells to construct embryonic arrays, the function unit of which can act in three different operating modes. Compared with cells based on LUT with four inputs and one output, the new architecture displays improved flexibility and resource utilization ratios. Configuration memory employed by embryonics can implement 1-bit error correcting and 2-bit error checking by using extended hamming code. The two-level fault-tolerance is achieved in the embryonic array by the error correcting mechanism of memory at cell-level and column-elimination mechanism at array-level which is triggered by cell-level fault detection. The implementation and simulation of a 4-bit adder subtracter circuit is presented as a practical example to show the effectiveness of embryonic arrays in terms of functionality and two-level fault-tolerance.