A DSP based 10BaseT/100BaseTX ethernet transceiver in a 1.8V, 0.18um CMOS technology

被引：8

作者：

Huss, S ^{[1
]}

Mullen, M ^{[1
]}

Gray, CT ^{[1
]}

Smith, R ^{[1
]}

Summers, M ^{[1
]}

Shafer, J ^{[1
]}

Heron, P ^{[1
]}

Sawinska, T ^{[1
]}

Medero, J ^{[1
]}

机构：

[1] Tality Corp, Analog & Mixed Signal Design Ctr, Cary, NC USA

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929741

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a DSP based 10BaseT/100BaseTX ethernet physical layer interface in a 1.8V 0.18 mu m single poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths > 150m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6mm(2) and consumes 350 mW of power.

引用

页码：135 / 138

页数：4

共 4 条

[1] A 10Gbase Ethernet Transceiver (LAN PHY) in a 1.8V, 0.18um SOI/CMOS technology
Yoshimura, T
Ueda, K
Takasoh, J
Wada, Y
Oka, T
Kondoh, H
Chiba, O
Azekawa, Y
Ishiwaki, M
PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2002, : 355 - 358
[2] A 10 Gbase Ethernet Transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology
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Ueda, K
Takasoh, J
Kondoh, H
IEICE TRANSACTIONS ON ELECTRONICS, 2003, E86C (04) : 643 - 651
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[4] Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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2013 IEEE 8TH NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC), 2013, : 78 - 80

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