A DSP based 10BaseT/100BaseTX ethernet transceiver in a 1.8V, 0.18um CMOS technology

被引：8

作者：

Huss, S ^{[1
]}

Mullen, M ^{[1
]}

Gray, CT ^{[1
]}

Smith, R ^{[1
]}

Summers, M ^{[1
]}

Shafer, J ^{[1
]}

Heron, P ^{[1
]}

Sawinska, T ^{[1
]}

Medero, J ^{[1
]}

机构：

[1] Tality Corp, Analog & Mixed Signal Design Ctr, Cary, NC USA

来源：

PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2001年

关键词：

D O I：

10.1109/CICC.2001.929741

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a DSP based 10BaseT/100BaseTX ethernet physical layer interface in a 1.8V 0.18 mu m single poly 5-level metal CMOS technology. The DSP architecture allows for robust performance for cable lengths > 150m. The integrated transceiver is IEEE 802.3 compliant and uses existing 1:1 transformers. The active area is 6.6mm(2) and consumes 350 mW of power.

引用

页码：135 / 138

页数：4

共 6 条

[1]

[Anonymous], 1995, 8023U1995 IEEE, V1, P415, DOI [10.1109/IEEESTD.1995.7974916, DOI 10.1109/IEEESTD.1995.7974916]

[2] A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet [J].

Everitt, J ;

Parker, JF ;

Hurst, P ;

Nack, D ;

Konda, KR .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :2169-2177

[3]

KELLY NP, 2000, P IEEE INT SOL STAT, P310

[4] TIMING RECOVERY IN DIGITAL SYNCHRONOUS DATA RECEIVERS [J].

MUELLER, KH ;

MULLER, M .

IEEE TRANSACTIONS ON COMMUNICATIONS, 1976, 24 (05) :516-531

[5]

MULLEN J, 1999, P IEEE MIDW S CIRC S

[6]

SHOAEI O, 2000, P IEEE SOL STAT CIRC, P308

← 1 →