Comparative Power Analysis of CMOS & Adiabatic Logic Gates

被引：0

作者：

Sharma, Himanshi ^{[1
]}

Singh, Rajan ^{[1
]}

机构：

[1] Noida Inst Engn Technol, ECE, Greater Noida, India

来源：

2015 INTERNATIONAL CONFERENCE ON GREEN COMPUTING AND INTERNET OF THINGS (ICGCIOT) | 2015年

关键词：

CMOS; Adiabatic Logic; Inverter; NAND; XOR; Power Consumption; LEAKAGE CURRENT; MINIMIZATION;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The present paper proposes the comparative power analysis of different logic gates using conventional CMOS Designs and adiabatic clock gating based designs. For achieving high performance, Adiabatic logic gates are designed using CPAL (complementary pass transistor adiabatic logic). The design of INVERTER, NAND and XOR has been simulated and verified. All the circuits have been simulated using 90nm technology. In comparison to conventional CMOS designs, adiabatic technology based designs consumes much less power and saves energy.

引用

页码：7 / 11

页数：5

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