Asymmetrical Length Biasing for Energy Efficient Digital Circuits

被引：0

作者：

Veirano, Francisco ^{[1
]}

Silveira, Fernando ^{[1
]}

Naviner, Lirida ^{[2
]}

机构：

[1] Univ Republica, Fac Ingn, Inst Ingn Elect, Montevideo, Uruguay

[2] Univ Paris Saclay, CNRS, Telecom ParisTech, LTCI, F-75013 Paris, France

来源：

2017 IEEE 8TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS) | 2017年

关键词：

OPERATION; PROCESSOR; DESIGN; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies that minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results show that by using this sizing methodology, the energy per operation can be reduced more than 50% in a wide range of target performances. We used a 28nm UTBB FDSOI technology and we show that the combination of supply voltage scaling, back plane biasing and length biasing can be combined to obtain extremely energy efficient digital circuits.

引用

页数：4

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