Emulating and Diagnosing IR-Drop by Using Dynamic SDF

被引:0
作者
Peng, Ke [1 ]
Huang, Yu [2 ]
Guo, Ruifeng [2 ]
Cheng, Wu-Tung [2 ]
Tehranipoor, Mohammad [1 ]
机构
[1] Univ Connecticut, ECE Dept, Storrs, CT 06269 USA
[2] Univ Connecticut, Mentor Graphics, Storrs, CT 06269 USA
来源
2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010) | 2010年
关键词
D O I
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中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The Standard Delay Format (SDF) information is very important in timing-aware simulation of VLSI designs. However, conventionally, SDF is only design-dependent, but pattern-independent, which is called static SDF in this paper. Static SDF ignores all dynamic pattern dependent parameters, such as IR drop and crosstalk. In this paper, we propose a novel pattern-dependent SDF (called dynamic SDF) generation technique, and apply it to take IR-drop effects into consideration. With the proposed IR-drop-aware SDF generation technique, we improve the accuracy of simulation, and perform diagnosis on the failed patterns to pin point the pattern-dependent IR-drop defects in our design. Experimental results demonstrate the efficiency of this method when used for transition delay fault pattern application and diagnosis.
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收藏
页码:503 / +
页数:2
相关论文
共 18 条
[1]  
AHMED N., 2007, P DES AUT C DAC 07
[2]   Supply voltage noise aware ATPG for transition delay faults [J].
Ahmed, Nisar ;
Tehranipoor, Mohammad ;
Jayaram, Vinay .
25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, :179-+
[3]   Analysis of IR-drop scaling with implications for deep submicron P/G network designs [J].
Ajami, AH ;
Banerjee, K ;
Mehrotra, A ;
Pedram, M .
4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, :35-40
[4]  
[Anonymous], US MAN SYN TOOLS VER
[5]  
[Anonymous], IEEE INT TEST C ITC
[6]  
*CAD INC, 2008, CAD ENC MAN
[7]  
HSU C, DAC 2006
[8]  
LEE J., 2008, P DES AUT TEST EUR D
[9]   Effect of IR-Drop on path delay testing using statistical analysis [J].
Liu, Chunsheng ;
Wu, Yang ;
Huang, Yu .
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM, 2007, :245-+
[10]  
MA J., 2009, P IEEE VLSI TEST S V