YaNoC: Yet another Network-on-Chip Simulation Acceleration Engine using FPGAs

被引：9

作者：

Prasad, Prabhu B. M. ^{[1
]}

Parane, Khyamling ^{[1
]}

Talawar, Basavaraj ^{[1
]}

机构：

[1] Natl Inst Technol Karnataka, SPARK Lab, Mangalore, India

来源：

2018 31ST INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2018 17TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID & ES) | 2018年

关键词：

Network-on-Chip; NoC; FPGA; Simulation acceleration; Custom topology;

D O I：

10.1109/VLSID.2018.39

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present an FPGA based NoC simulation framework, YaNoC, that supports the creation of standard and custom topologies, design of routing algorithms, generation of various synthetic traffic patterns, and exploration of a full set of microarchitectural parameters. The framework supports all standard minimal routing algorithms for conventional NoCs and implements table based routing to support the creation of new routing algorithm. A custom topology called Diagonal Mesh (DMesh) has been evaluated using table based and a modified version of the XY routing algorithm. Mesh and DMesh topologies saturate at the injection rates of 45 % and 55 %. We find that the Table based routing implementation consumes 0.98x fewer hardware resources than the conventional XY routing. We observed the speedup of 2548x compared to the Booksim software simulator. YaNoC achieves speedup of 2.54x and 25x with respect to CONNECT and DART FPGA based NoC simulators.

引用

页码：67 / 72

页数：6

共 12 条

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