Reducing switching activity on datapath buses with control-signal gating

被引:26
作者
Kapadia, H [1 ]
Benini, L
De Micheli, G
机构
[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA
[2] Univ Bologna, DEIS, Bologna, Italy
基金
美国国家科学基金会;
关键词
clock gating; control signal gating; data buses; datapaths; logic synthesis; low power; power management; switching activity;
D O I
10.1109/4.748193
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a technique for saving power dissipation in large datapaths by reducing unnecessary switching activity on buses. The focus of the technique is on achieving effective power savings with minimal overhead. When a bus is not going to be used in a datapath, it is held in a quiescent state by stopping the propagation of switching activity through the module(s) driving the bus, The "observability don't-care condition" of a bus is defined to detect unnecessary switching activity on the bus. This condition is used to gate control signals going to the bus-driver modules so that switching activity on the module inputs does not propagate to the bus. A methodology for automatically synthesizing gated control signals from the register-transfer-level description of a design is presented. The technique has very low area, delay, power, and designer effort overhead, It was applied to one of the integer execution units of a 64-bit, two-way superscalar RISC microprocessor. Experimental results from running various application programs on the microprocessor show an average of 26.6% reduction in dynamic switching power in the execution unit, with no increase in critical path delay and negligible area overhead.
引用
收藏
页码:405 / 414
页数:10
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