共 11 条
- [2] Accurate high level datapath power estimation [J]. EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS, 1997, : 590 - 596
- [3] DHILLON YS, 2003, COMPUTER AIDED DES 2, P693
- [4] GOPALAKRISHNAN C, 2003, P 16 INT C JAN, V4, P297
- [5] KAUSHIK R, 2000, LOW POWER CMOLS VLSI, P2
- [7] KUMAR A, 1999, P 1999 IEEE INT S CI, V1, P66
- [9] Srivastava A, 2003, ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, P400, DOI 10.1109/ASPDAC.2003.1195048
- [10] Improving the efficiency of power simulators by input vector compaction [J]. 33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 165 - 168