Power optimization in data-path scheduling and binding with multiple supply voltages and threshold voltages by simulated annealing

被引:0
作者
Huang, JF [1 ]
Bian, JN [1 ]
Liu, ZP [1 ]
Wang, YF [1 ]
机构
[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
来源
2005 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS: VOL 1: COMMUNICATION THEORY AND SYSTEMS | 2005年
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We present a scheme to optimize power consumption in data-path scheduling and binding with resources operating at multiple supply voltages and threshold voltages by simulated annealing. The proposed scheme considers both scheduling and binding simultaneously such that we will have a wider solution space to explore and a solution with much lower power can be obtained. Besides, we give a more accurate high-level power model that not only the dynamic and leakage power of function units but also the sharing of function units is taken into account. Experimental results on a number of high-level benchmark circuits using three supply voltage and threshold voltage levels show that an average power savings of about 68% can be obtained compared to using a single supply and threshold voltage level (with a time constraint of 1.2 times the critical path delay and a resource constraint of two function units each type).
引用
收藏
页码:1370 / 1374
页数:5
相关论文
共 11 条
  • [1] Energy minimization using multiple supply voltages
    Chang, JM
    Pedram, M
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1997, 5 (04) : 436 - 443
  • [2] Accurate high level datapath power estimation
    Crenshaw, JE
    Sarrafzadeh, M
    [J]. EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS, 1997, : 590 - 596
  • [3] DHILLON YS, 2003, COMPUTER AIDED DES 2, P693
  • [4] GOPALAKRISHNAN C, 2003, P 16 INT C JAN, V4, P297
  • [5] KAUSHIK R, 2000, LOW POWER CMOLS VLSI, P2
  • [6] Leakage power analysis and reduction during behavioral synthesis
    Khouri, KS
    Jha, NK
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (06) : 876 - 885
  • [7] KUMAR A, 1999, P 1999 IEEE INT S CI, V1, P66
  • [8] A low power scheduling scheme with resources operating at multiple voltages
    Manzak, A
    Chakrabarti, C
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (01) : 6 - 14
  • [9] Srivastava A, 2003, ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, P400, DOI 10.1109/ASPDAC.2003.1195048
  • [10] Improving the efficiency of power simulators by input vector compaction
    Tsui, CY
    Marculescu, R
    Marculescu, D
    Pedram, M
    [J]. 33RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 1996, 1996, : 165 - 168