Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture

被引：10

作者：

Lu, Hongliang ^{[1
]}

Lu, Bin ^{[1
]}

Zhang, Yuming ^{[1
]}

Zhang, Yimen ^{[1
]}

Lv, Zhijun ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Key Lab Wide Band Gap Semicond Technol, Xian 710071, Shaanxi, Peoples R China

来源：

NANOMATERIALS | 2019年 / 9卷 / 02期

关键词：

TFET; BTBT; InAs/Si; heterojunction; staggered-bandgap; source-pocket; 2D Poisson equations; parabolic approximation; Kane's model; current model; IMPACT;

D O I：

10.3390/nano9020181

中图分类号：

O6 [化学];

学科分类号：

0703 ;

摘要：

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

引用

页数：11

共 28 条

[1] Realization of Silicon nanotube tunneling FET on junctionless structure using single and multiple gate workfunction [J].

Ambika, R. ;

Keerthana, N. ;

Srinivasan, R. .

SOLID-STATE ELECTRONICS, 2017, 127 :45-50

[2] Alloy Engineered Nitride Tunneling Field-Effect Transistor: A Solution for the Challenge of Heterojunction TFETs [J].

Ameen, Tarek A. ;

Ilatikhameneh, Hesameddin ;

Fay, Patrick ;

Seabaugh, Alan ;

Rahman, Rajib ;

Klimeck, Gerhard .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2019, 66 (01) :736-742

[3]

[Anonymous], 2013, SENT DEV UGUID, P400

[4] Trap-Assisted Tunneling in Si-InAs Nanowire Heterojunction Tunnel Diodes [J].

Bessire, Cedric D. ;

Bjoerk, Mikael T. ;

Schmid, Heinz ;

Schenk, Andreas ;

Reuter, Kathleen B. ;

Riel, Heike .

NANO LETTERS, 2011, 11 (10) :4195-4199

[5] Si-InAs heterojunction Esaki tunnel diodes with high current densities [J].

Bjork, M. T. ;

Schmid, H. ;

Bessire, C. D. ;

Moselund, K. E. ;

Ghoneim, H. ;

Karg, S. ;

Lortscher, E. ;

Riel, H. .

APPLIED PHYSICS LETTERS, 2010, 97 (16)

[6] Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing [J].

Chang, Hsu-Yu ;

Adams, Bruce ;

Chien, Po-Yen ;

Li, Jiping ;

Woo, Jason C. S. .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (01) :92-96

[7] Switching Mechanism and the Scalability of Vertical-TFETs [J].

Chen, Fan ;

Ilatikhameneh, Hesameddin ;

Tan, Yaohua ;

Klimeck, Gerhard ;

Rahman, Rajib .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (07) :3065-3068

[8] Impact of source-pocket engineering on device performance of dielectric modulated tunnel FET [J].

Das, Gyan Darshan ;

Mishra, Guru Prasad ;

Dash, Sidhartha .

SUPERLATTICES AND MICROSTRUCTURES, 2018, 124 :131-138

[9] Vertical Transistors Based on 2D Materials: Status and Prospects [J].

Giannazzo, Filippo ;

Greco, Giuseppe ;

Roccaforte, Fabrizio ;

Sonde, Sushant S. .

CRYSTALS, 2018, 8 (02)

[10] Tunnel field-effect transistors as energy-efficient electronic switches [J].

Ionescu, Adrian M. ;

Riel, Heike .

NATURE, 2011, 479 (7373) :329-337

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