Architectural breakdown of end-to-end latency in a TCP/IP network

被引：5

作者：

Larsen, Steen ^{[1
]}

Sarangam, Parthasarathy ^{[1
]}

Huggahalli, Ram ^{[1
]}

机构：

[1] Intel Corp, Santa Clara, CA 95051 USA

来源：

19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/SBAC-PAD.2007.33

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-end latency. The overheads of typical software based protocol stacks on CPU utilization and throughput have been well evaluated in several recent studies. In this paper, we focus on end-to-end latency and present a detailed characterization across typical server system hardware and software stack components. We demonstrate that application level end-to-end latency with a 10GbE connection can be as low as 10 microseconds for a single isolated request. The paper analyzes the components of the latency and discusses possible significant variations to the components under realistic conditions. We note that methods that are used to optimize throughput can often be responsible for the perception that Ethernet based latencies can be very high. Methods to pursue reducing the minimum latency and controlling the variations are presented.

引用

页码：195 / 202

页数：8