A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications

被引:37
作者
Kumar, Sandeep [1 ]
Mukherjee, Atin [1 ]
机构
[1] Natl Inst Technol Rourkela, Dept Elect & Commun, Rourkela 769008, Odisha, India
关键词
Latches; Robustness; Feedback loop; Transient analysis; Inverters; Resilience; Single event upsets; Double-node upset; radiation-hardened latch; robustness; self-healing; soft errors; FAULT-TOLERANCE; DESIGN;
D O I
10.1109/TVLSI.2021.3110135
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This work presents a single event double node upset (SEDNU) self-healing (DNUSH) latch to meet the high-robustness requirement of the applications used in a harsh radiation environment. The DNUSH latch is based on dual modular redundancy and mainly employs C-elements and inverters, forming multi-feedback interlocked loops to retain the correct data even after the radiation event. The self-healing capability of the proposed latch is successfully shown by the fault injection simulation using Synopsys HSPICE. Simulation results show that the proposed latch can self-heal from all SEDNUs, consumes low power even for high-speed operations, and has the least power-delay-area product (PDAP) compared to the existing SEDNU resilient latches. The proposed latch offers on average 51.25% improvement in speed, 22.67% saving in power consumption, and 59.74% lower PDAP compared to the existing SEDNU resilient latches. In addition, the sensitivity assessment of the proposed latch against the process, voltage, and temperature (PVT) variations are found to be either low or equivalent to the reference latches.
引用
收藏
页码:2076 / 2085
页数:10
相关论文
共 33 条
[1]   Non-Volatile Spintronic Flip-Flop Design for Energy-Efficient SEU and DNU Resilience [J].
Alghareb, Faris S. ;
Zand, Ramtin ;
DeMara, Ronald F. .
IEEE TRANSACTIONS ON MAGNETICS, 2019, 55 (03)
[2]   Variations in Nanometer CMOS Flip-Flops: Part I-Impact of Process Variations on Timing [J].
Alioto, Massimo ;
Consoli, Elio ;
Palumbo, Gaetano .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (08) :2035-2043
[3]   Understanding the Effect of Process Variations on the Delay of Static and Domino Logic [J].
Alioto, Massimo ;
Palumbo, Gaetano ;
Pennisi, Melita .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 18 (05) :697-710
[4]   Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction [J].
Black, Jeffrey D. ;
Dodd, Paule E. ;
Warren, Kevin M. .
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2013, 60 (03) :1836-1851
[5]  
Eftaxiopoulos N., 2015, PROC IEEE 58 INT MID, P1
[6]   DONUT: A Double Node Upset Tolerant Latch [J].
Eftaxiopoulos, Nikolaos ;
Axelos, Nicholas ;
Pekmestzi, Kiamal .
2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2015, :509-514
[7]   Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies [J].
Fazeli, M. ;
Miremadi, S. G. ;
Ejlali, A. ;
Patooghy, A. .
IET COMPUTERS AND DIGITAL TECHNIQUES, 2009, 3 (03) :289-303
[8]   Soft Errors Induced by High-Energy Electrons [J].
Gadlage, Matthew J. ;
Roach, Austin H. ;
Duncan, Adam R. ;
Williams, Aaron M. ;
Bossev, Dobrin P. ;
Kay, Matthew J. .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2017, 17 (01) :157-162
[9]   Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology [J].
Guo, Jing ;
Zhu, Lei ;
Liu, Wenyi ;
Huang, Hai ;
Liu, Shanshan ;
Wang, Tianqi ;
Xiao, Liyi ;
Mao, Zhigang .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (05) :1593-1600
[10]   Soft error interception latch: double node charge sharing SEU tolerant design [J].
Katsarou, K. ;
Tsiatouhas, Y. .
ELECTRONICS LETTERS, 2015, 51 (04) :330-331