Multi-Mode Unrolled Architectures for Polar Decoders

被引:25
|
作者
Giard, Pascal [1 ]
Sarkis, Gabi [1 ]
Thibeault, Claude [2 ]
Gross, Warren J. [1 ]
机构
[1] McGill Univ, Dept Elect & Comp Engn, Montreal, PQ H3A 0G4, Canada
[2] Ecole Technol Super, Dept Elect Engn, Montreal, PQ H3C 1K3, Canada
关键词
ASIC; high throughput; multi-mode; polar codes; unrolled architecture; SUCCESSIVE-CANCELLATION DECODER; CODES;
D O I
10.1109/TCSI.2016.2586218
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we present a family of architectures for polar decoders using a reduced-complexity successive-cancellation decoding algorithm that employs unrolling to achieve extremely high throughput values while retaining moderate implementation complexity. The resulting fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput in excess of 1 Tbps on a 65 nm ASIC at 500 MHz-three orders of magnitude greater than current state-of-the-art polar decoders. However, unrolled decoders are built for a specific, fixed code. Therefore we also present a new method to enable the use of multiple code lengths and rates in a fully-unrolled polar decoder architecture. This method leads to a length-and rate-flexible decoder while retaining the very high speed typical to unrolled decoders. The resulting decoders can decode a master polar code of a given rate and length, and several shorter codes of different rates and lengths. We present results for two versions of a multi-mode decoder supporting eight and ten different polar codes, respectively. Both are capable of a peak throughput of 25.6 Gbps. For each decoder, the energy efficiency for the longest supported polar code is shown to be of 14.8 pJ/bit at 250 MHz and of 8.8 pJ/bit at 500 MHz.
引用
收藏
页码:1443 / 1453
页数:11
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