A run-time reconfigurable 2D discrete wavelet transform using JBits

被引：1

作者：

Ballagh, J ^{[1
]}

Athanas, P ^{[1
]}

Keller, E ^{[1
]}

机构：

[1] Virginia Tech, Blacksburg, VA 24061 USA

来源：

RECONFIGURABLE TECHNOLOGY: FPGAS AND RECONFIGURABLE PROCESSORS FOR COMPUTING AND COMMUNICATIONS III | 2001年 / 4525卷

关键词：

wavelets; DWT; compression; RTR; JBits; FPGA;

D O I：

10.1117/12.434374

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With the growth in high performance multimedia applications, specialized hardware for certain tasks is desirable. While ASICs provide a solution addressing performance, they are unable to provide an optimal solution for a given problem instance. FPGAs can be used with run-time reconfiguration to dynamically customize a circuit. Optimizations leading to faster circuits and reduced logic can result. The paper discusses the implementation of a run-time parameterizable 2D Discrete Wavelet Transform core using the JBits tool suite. The motivation for such a core is discussed. as well the benefits afforded by dynamic circuit specialization.

引用

页码：116 / 124

页数：9

共 27 条

[1]

BALLAGH J, 2001, 8 REC ARCH WORKSH SA

[2]

BALLAGH J, 2001, 1 ENG REC SYST ALG L

[3]

BENKRID A, 2001, IEEE S FPGAS CUST CO

[4]

BURNS J, 1997, IEEE S FPGAS CUST CO, P66

[5] Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform [J].

Chakrabarti, C ;

Mumford, C .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (03) :289-298

[6] Architectures for wavelet transforms: A survey [J].

Chakrabarti, C ;

Vishwanath, M ;

Owens, RM .

JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1996, 14 (02) :171-192

[7]

CHAPMAN K, 1994, ELECT DESIGN NE 0512

[8]

COURTNEY T, 2000, LECT NOTES COMPUTER, V1896

[9]

Croisier A., 1976, INT C INF SCI SYST

[10] THE WAVELET TRANSFORM, TIME-FREQUENCY LOCALIZATION AND SIGNAL ANALYSIS [J].

DAUBECHIES, I .

IEEE TRANSACTIONS ON INFORMATION THEORY, 1990, 36 (05) :961-1005

← 1 2 3 →