A Sizing Methodology for Rise-Time Minimization of Dickson Charge Pumps With Capacitive Loads

被引：14

作者：

Saeed, Ahmed ^{[1
]}

Ibrahim, Sameh ^{[1
]}

Ragai, Hani Fikry ^{[1
]}

机构：

[1] Ain Shams Univ, Dept Elect & Comp Engn, Cairo 11566, Egypt

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2017年 / 64卷 / 10期

关键词：

Design methodology; switched-capacitor DC-DC converters; charge pump; rise time; CMOS TECHNOLOGY;

D O I：

10.1109/TCSII.2017.2687864

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel sizing methodology for Dickson charge pumps with pure capacitive loads is presented. The methodology is based on dynamic analysis to minimize the rise time of the charge pump up to 25% under a given circuit area. The methodology is validated through the implementation of a sixstage charge pump-based driver in 180-nm standard low-voltage CMOS technology. The driver is used for the excitation of ultrasonic transducers with 34 V at a resonance frequency of 220 KHz. A rise time of only 512 nS is achieved. The driver consumes 10.6 mA drawn from a 5-V supply at a pumping frequency of 50 MHz and occupies an area of 0.2 mm(2).

引用

页码：1202 / 1206

页数：5