Design of Low Power, High Speed, Low Offset and Area Efficient Dynamic-Latch Comparator for SAR-ADC

High-speed analog to digital converters (ADCs), sense amplifiers of memories, RFID applications and data-receiver-designs employ wide variety of dynamic comparators. This paper presents an improved design for a dynamic-latchbased comparator while achieving area-efficient realization at lower power dissipation with low offset. The comparator has two different stages: those of a dynamic differential input gain stage and an output latch. The proposed circuit has been designed for successive approximation register (SAR) - ADC's and simulated using UMC 180 nm standard CMOS-Process to operate on 100 MHz clock, at 1.8V supply voltage. The resolution has been set at 50 mV. Design and simulation have been carried out using CADENCE Virtuoso EDA tool.