Stencil mask ion implantation technology for high performance MOSFETs.

被引：4

作者：

Shibata, T ^{[1
]}

Suguro, K ^{[1
]}

Sugihara, K ^{[1
]}

Mizuno, H ^{[1
]}

Yagishita, A ^{[1
]}

Saito, T ^{[1
]}

Okumura, K ^{[1
]}

Nishihashi, T ^{[1
]}

Gotou, T ^{[1
]}

Tsunoda, M ^{[1
]}

Saji, S ^{[1
]}

机构：

[1] Toshiba Corp, Semicond Co, Proc & Mfg Engn Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST | 2000年

关键词：

D O I：

10.1109/IEDM.2000.904456

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel stencil mask ion implantation technology for simplifying the sequence of steps involved in implantation process is introduced. The experiment to evaluation of stencil mask implantation showed varity of pattern of implanted region which can be connected using stencil masks. The advantage of such an impnatation is that the different impanted conditions can be easily acheived. Applicationof stencil mask implantation techology is performed on damascene netal gate MOSFET fabrication technique.

引用

页码：869 / 871

页数：3