A Many-core Architecture for In-Memory Data Processing

被引：20

作者：

Agrawal, Sandeep R. ^{[1
]}

Idicula, Sam ^{[1
]}

Raghavan, Arun ^{[1
]}

Vlachos, Evangelos ^{[1
]}

Govindaraju, Venkatraman ^{[1
]}

Varadarajan, Venkatanathan ^{[1
]}

Balkesen, Cagri ^{[1
]}

Giannikis, Georgios ^{[1
]}

Roth, Charlie ^{[1
]}

Agarwal, Nipun ^{[1
]}

Sedlar, Eric ^{[1
]}

机构：

[1] Oracle Labs, Burlington, MA 01803 USA

来源：

50TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO) | 2017年

关键词：

Accelerator; Big data; Microarchitecture; Databases; DPU; Low power; Analytics Processor; In-Memory Data Processing; Data Movement System; SUPPORT; VISION;

D O I：

10.1145/3123939.3123985

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

For many years, the highest energy cost in processing has been data movement rather than computation, and energy is the limiting factor in processor design [21]. As the data needed for a single application grows to exabytes [56], there is clearly an opportunity to design a bandwidth-optimized architecture for big data computation by specializing hardware for data movement. We present the Data Processing Unit or DPU, a shared memory many-core that is specifically designed for high bandwidth analytics workloads. The DPU contains a unique Data Movement System (DMS), which provides hardware acceleration for data movement and partitioning operations at the memory controller that is sufficient to keep up with DDR bandwidth. The DPU also provides acceleration for core to core communication via a unique hardware RPC mechanism called the Atomic Transaction Engine. Comparison of a DPU chip fabricated in 40nm with a Xeon processor on a variety of data processing applications shows a 3x-15x performance per watt advantage.

引用

页码：245 / 258

页数：14

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