Pinch-Off Voltage Lowering in Polycrystalline Silicon Thin-Film Transistors

Pinch-off voltage (V-p) lowering phenomenon in the output characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is reported and investigated by measurement and device simulation. As the trap density increases, the observed V-p becomes smaller than the ideal V-p while maintaining a linear relationship with the gate-source voltage (V-gs). The device simulation analysis revealed two mechanisms for V-p lowering. One is current saturation due to the increase in onset gate-drain voltage (V-gd), causing the drain region to become highly resistive, which originates from the gradual increase in surface potential with V-gs. This is interpreted as an expansion of the conventional pinch-off concept. The other is the current limitation, controlled by grain boundary (GB) and intragrain conductance at the drain edge, which is peculiar to poly-Si TFTs. On the basis of the above analysis, a GB-conductance-limited carrier transport model is proposed. Its good agreement with the measurements suggests the suitability of this model for describing V-p lowering. (C) 2011 The Japan Society of Applied Physics