Functional decomposition with application to LUT-based FPGA synthesis

被引:0
|
作者
Qiao, J [1 ]
Asada, K
机构
[1] Univ Tokyo, Grad Sch Elect Engn, Tokyo 1138656, Japan
[2] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 1138656, Japan
关键词
logic synthesis; functional decomposition; compatibility class encoding; LUT-based FPCAs;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper. we deal with the problem of compatibility class encoding, and propose a novel algorithm for finding a good functional decomposition with application to LUT-based FPGA synthesis. Based on exploration of the design space, we concentrate on extracting a set of <(<alpha>)over right arrow> components, which can be merged into the minimum number of multiple-output CLBS or LUTs, such that the decomposition constructed from these components is also minimal. In particular, to explore more degrees of freedom, we introduce pliable encoding to take over the conventional rigid encoding when it fails to find a satisfactory decomposition by rigid encoding. Experimental results on a large set of MCNC91 logic synthesis benchmarks show that our method is quite promising.
引用
收藏
页码:2004 / 2013
页数:10
相关论文
共 50 条
  • [1] Functional decomposition with application to LUT-based FPGA synthesis
    Qiao, Jian
    Asada, Kunihiro
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2001, E84-A (08) : 2004 - 2013
  • [2] Finding an optimal functional decomposition for LUT-based FPGA synthesis
    Qiao, J
    Ikeda, M
    Asada, K
    PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 225 - 230
  • [3] Methods of logical functions decomposition for LUT-based FPGA
    Bouchard, S
    Diou, A
    IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE 98) - PROCEEDINGS, VOLS 1 AND 2, 1998, : 487 - 492
  • [4] Carry circuitry for LUT-based FPGA
    Jindal, V
    Agarwal, A
    17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 731 - 734
  • [5] Logic synthesis of low power FSM for LUT-based FPGA
    Kubica, Marcin
    Kajstura, Krzysztof
    Kania, Dariusz
    INTERNATIONAL CONFERENCE OF COMPUTATIONAL METHODS IN SCIENCES AND ENGINEERING 2018 (ICCMSE-2018), 2018, 2040
  • [6] BMB synthesis of binary functions using symbolic functional decomposition for LUT-based FPGAs
    Wisniewski, Mariusz
    Deniziak, Stanislaw
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2018, 120 : 16 - 22
  • [7] Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time
    Veredas, Francisco-Javier
    Scheppler, Michael
    Pfleiderer, Hans-Joerg
    2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS, 2006, : 1371 - +
  • [8] LUT-Based FPGA Technology Mapping for Reliability
    Cong, Jason
    Minkovich, Kirill
    FPGA 10, 2010, : 288 - 288
  • [9] LUT-Based FPGA and its CAD techniques
    Peng, Yuxing
    Chen, Shuming
    Chen, Fujie
    Dongli Gongcheng/Power Engineering, 18 (06): : 1 - 5
  • [10] LUT-Based FPGA Technology Mapping for Reliability
    Cong, Jason
    Minkovich, Kirill
    PROCEEDINGS OF THE 47TH DESIGN AUTOMATION CONFERENCE, 2010, : 517 - 522