The role of sub-interpolation for Delay-Line Time-to-Digital Converters in FPGA devices

Most of the Time-to-Digital Converters (TDCs) implemented in Field Programmable Gate Array (FPGA) devices are based on Tapped Delay Lines (TDLs). This solution makes mandatory the implementation of sub-interpolation procedures in the processing flow in order to mitigate effects of the different characteristics of the FPGA resources used. Specifically, we focus issues of the sub-interpolation topic also still outstanding and realize the experimental comparison of the state-of-art techniques, providing design rules for their optimal implementation. According to the host electronic device, the paper reveals the design rules to get the best performance, by using known sub-interpolation techniques but introducing criteria of choice and design procedures never presented in literature. These are fundamental for the most proper and useful application of sub-interpolation techniques in designing high-performance TDCs.