Effects of the NoC Architecture in the Performance of NoC-based MPSoCs

被引：0

作者：

Silva, Douglas R. G. ^{[1
]}

Oliveira, Bruno S. ^{[1
]}

Moraes, Fernando G. ^{[1
]}

机构：

[1] PUCRS Univ, Dept Comp Sci, Porto Alegre, RS, Brazil

来源：

2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2014年

关键词：

NoC-based MPSoC; NoCs; routing; topology; performance evaluation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The goal of this work is to evaluate the impact of multiple Network-on-Chip (NoC) architectural parameters over the performance of applications running on Multiprocessors Systems-on-Chip (MPSoCs) using message passing as communication protocol. Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs, therefore, the adoption of NoCs is a trend for the communication infrastructure in MPSoCs due to their performance compared to bus-based architectures and scalability compared to crossbar-based architectures. However, there is an important gap in the literature with works evaluating the impact of NoC parameters in the performance of applications running in MPSoCs. This work proposes the evaluation of how different NoC parameters affect applications running in a real MPSoC, trying to answer the following question: how does a given NoC parameter affect the performance of the MPSoC?

引用

页码：431 / 434

页数：4

共 10 条

[1]

Castilhos Guilherme, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI. Emerging VLSI Technologies and Architectures (ISVLSI), P153, DOI 10.1109/ISVLSI.2013.6654651

[2] The odd-even turn model for adaptive routing [J].

Chiu, GM .

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2000, 11 (07) :729-738

[3]

Garibotti R., 2013, DAC

[4]

GLASS CJ, 1992, ACM COMP AR, V20, P278, DOI 10.1145/146628.140384

[5]

KUMAR R, 2013, ICICDT, P215

[6] Application-Aware Topology Reconfiguration for On-Chip Networks [J].

Modarressi, Mehdi ;

Tavakkol, Arash ;

Sarbazi-Azad, Hamid .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (11) :2010-2022

[7] Power-efficient deterministic and adaptive routing in torus networks-on-chip [J].

Rahmati, Dara ;

Sarbazi-Azad, Hamid ;

Hessabi, Shaahin ;

Kiasari, Abbas Eslami .

MICROPROCESSORS AND MICROSYSTEMS, 2012, 36 (07) :571-585

[8]

Singh A. K., 2013, DAC

[9] A Design Space Exploration Methodology for Application Specific MPSoC Design [J].

Singh, Amit Kumar ;

Kumar, Akash ;

Srikanthan, Thambipillai .

2011 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2011, :339-+

[10]

Zou Y, 2013, INT SYM QUAL ELECT, P643, DOI 10.1109/ISQED.2013.6523678

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