Implementation and analysis of power consumption for a power optimized decimator designed for cascaded sigma-delta A/D converters

This paper presents the implementation and power analysis or an efficient decimator architecture for cascaded Sigma-Delta (Sigma Delta) modulators. The recombination logic for cascaded modulators in general and a gain error correction for continuous time (CT) modulators are integrated into the first decimation stage. An appropriate filter topology is derived and synthesized in a 0.18 mu m CMOS technology using SYNOPSYS DESIGN COMPILER. The power consumption of the various blocks is analyzed using stimuli or a SOFO Sigma Delta-modulator and SYNOPSYS PRIMEPOWER. A comparison of the proposed architecture to a conventional implementation shows a remarkable reduction or power consumption by a factor or 4.