Xetal-II: A 107 GOPS, 600 mW massively parallel processor for video scene analysis

被引:50
作者
Abbo, Anteneh A. [1 ]
Kleihorst, Richard P. [2 ]
Choudhary, Vishal [3 ]
Sevat, Leo [2 ]
Wielage, Paul [2 ]
Mouy, Sebastien [2 ]
Vermeulen, Bart [2 ]
Heijligers, Marc [2 ]
机构
[1] Philips Res, NL-5656 AE Eindhoven, Netherlands
[2] NXP Semiconduct Res, NL-5656 AE Eindhoven, Netherlands
[3] NXP Semiconduct India Pvt Ltd, Bangalore 560045, Karnataka, India
关键词
low-power; parallel processing; processor tile; single-instruction multiple-data (SIMD); smart cameras; very large scale integration (VLSI); video scene analysis;
D O I
10.1109/JSSC.2007.909328
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm(2).
引用
收藏
页码:192 / 201
页数:10
相关论文
共 10 条
[1]  
ABBO A, 2002, P ADV CONC INT VIS S, P6
[2]  
Abbo AA, 2004, LECT NOTES COMPUT SC, V3254, P532
[3]  
[Anonymous], 2003, TR200396 MITS EL RES
[4]  
JONKER PP, 1994, INT C PATT RECOG, P334, DOI 10.1109/ICPR.1994.577193
[5]   Imagine: Media processing with streams [J].
Khailany, B ;
Dally, WJ ;
Kapasi, UJ ;
Mattson, P ;
Namkoong, J ;
Owens, JD ;
Towles, B ;
Chang, A ;
Rixner, S .
IEEE MICRO, 2001, 21 (02) :35-46
[6]  
KLEIHORST RP, 2001, P IEEE INT S CIRC SY, V5, P215
[7]   An integrated memory array processor architecture for embedded image recognition systems [J].
Kyo, S ;
Okazaki, S ;
Arai, T .
32ND INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, PROCEEDINGS, 2005, :134-145
[8]   Distinctive image features from scale-invariant keypoints [J].
Lowe, DG .
INTERNATIONAL JOURNAL OF COMPUTER VISION, 2004, 60 (02) :91-110
[9]  
Nakajima M., 2006, 2006 INT SOLID STATE, V49, P410
[10]   Core-based scan architecture for silicon debug [J].
Vermeulen, B ;
Waayers, T ;
Goel, SK .
INTERNATIONAL TEST CONFERENCE 2002, PROCEEDINGS, 2002, :638-647