IBM POWER6 microarchitecture

被引：135

作者：

Le, H. Q. ^{[1
]}

Starke, W. J. ^{[1
]}

Fields, J. S. ^{[1
]}

O'Connell, F. P. ^{[1
]}

Nguyen, D. Q. ^{[1
]}

Ronchetti, B. J. ^{[1
]}

Sauer, W. M. ^{[1
]}

Schwarz, E. M. ^{[1
]}

Vaden, M. T. ^{[1
]}

机构：

[1] IBM Syst & Technol Grp, Austin, TX 78758 USA

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2007年 / 51卷 / 06期

关键词：

D O I：

10.1147/rd.516.0639

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes the implementation of the IBM POWER6(TM) microprocessor, a two-way simultaneous multithreaded (SMT) dual-core chip whose keyfeatures include binary compatibility with IBM POWER5(TM) microprocessor-based systems; increased functional capabilities, such as decimal floating-point and vector multimedia extensions; significant reliability, availability, and serviceability enhancements; and robust scalability with up to 64 physical processors. Based on a new industry-leading high-frequency core architecture with enhanced SMT and driven by a high-throughput symmetric multiprocessing (SMP) cache and memory subsystem, the POWER6 chip achieves a significant performance boost compared with its predecessor, the POWER5 chip. Key extensions to the coherence protocol enable POWER6 microprocessor-based systems to achieve better SMP scalability while enabling reductions in system packaging complexity and cost.

引用

页码：639 / 662

页数：24

共 16 条

[1] IBM POWER6 partition mobility: Moving virtual servers seamlessly between physical systems [J].