Modular Data Link Layer Processing for THz communication

In this paper, we demonstrate a modular baseband and modular data link layer processors for wireless communication, which has been designed for a 200 GHz frontend. Although the individual system elements are well known, we combine the performance of parallel baseband and data link layer cores to cover a larger bandwidth. We combine three cores and achieve a single 1.5 GHz channel (3x500 MHz). This paper is focused on the digital elements of the demonstrator, especially on the data link layer aspects and field-programmable gate array (FPGA) processing. We discuss the performance of the back-to-back connected demonstrator, with the focus on the data link layer implementation that is included in the baseband chip. The peak data rate achieved by the presented demonstrator is 1920 Mbps. The solution uses forward error correction mechanisms based on convolutional codes at the code rate equal to 3/4 and accepts bit error rate (BER) up to 10(-2). Point-to-point and mesh network topologies are supported.