Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics

被引：9

作者：

Sun, JJ ^{[1
]}

Osburn, CM ^{[1
]}

机构：

[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1998年 / 45卷 / 06期

基金：

美国国家科学基金会;

关键词：

elevated source/drain; epi facet; MOSFET;

D O I：

10.1109/16.678583

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Deep submicron elevated source/drain (SID) MOSFET's with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using two-dimensional (2-D) process and device simulations. A slight degradation of drain-induced-barrier-lowering Delta V-t (DIBL) has been projected due to the locally deeper junction beneath the epi facets. The locally deeper junction also shortens the SID extension length if the spacer thickness is kept the same. The shorter extension in turn leads to a smaller parasitic resistance and therefore a higher device drive current. Gate-to-drain capacitance of the elevated S/D MOSFET is decreased as a result of faceting because of the reduced overlap area.

引用

页码：1377 / 1380

页数：4

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