A fault-tolerant 176 gbit solid state mass memory architecture

被引：2

作者：

Cardarilli, GC ^{[1
]}

Marinucci, P ^{[1
]}

Ottavi, M ^{[1
]}

Salsano, A ^{[1
]}

机构：

[1] Univ Roma Tor Vergata, Dept Elect Engn, Rome, Italy

来源：

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/DFTVS.2000.887155

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new Solid Stare Mass Memory (SSMM) suitable for space applications The memory reliability is increased by rising two different approaches. Firstly, memory mass fault-tolerance, with respect to hard failures, is obtained by using a fine-granularity hierarchical structure with a certain level of redundancy. A second strategy used for facing soft errors is based on Error Correction Codes (ECC) and periodic memory washing. A performance index has been developed for evaluating the main parameters of the SSMM architecture. This index rakes into account the ECC capability, the memory weight and reliability allowing to relate them to the required overhead.

引用

页码：173 / 180

页数：8