An analytic approach used to design a low power and low phase noise CMOS LC oscillator

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS LC oscillator is discussed. The phase noise performance for this kind of oscillator is predicted by using a simplified model. This method enables us to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the presented method is demonstrated by designing an LC CMOS oscillator in a 0.24 mu m CMOS technology. The predictions obtained from the derived expressions are in good agreement with simulation results over a wide range of the supply voltage.