A 2G/3G Cellular Analog Baseband Based on a Filtering ADC

被引：8

作者：

Sosio, Marco ^{[1
]}

Liscidini, Antonio ^{[1
]}

Castello, Rinaldo ^{[1
]}

机构：

[1] Univ Pavia, I-27100 Pavia, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2012年 / 59卷 / 04期

关键词：

Baseband (BB); dynamic range (DR); low-pass filters; out-of-band blockers; receivers; software-defined radio (SDR);

D O I：

10.1109/TCSII.2012.2188458

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entire baseband analog section of a Global System for Mobile Communications-Universal Mobile Telecommunications System (GSM-UMTS) reconfigurable receiver.

引用

页码：214 / 218

页数：5

共 13 条

[1] Toward multistandard mobile terminals - Fully integrated receivers requirements and architectures [J].

Brandolini, M ;

Rossi, P ;

Manstretta, D ;

Svelto, F .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2005, 53 (03) :1026-1038

[2]

Breems L., 2001, Continuous-Time Sigma Delta Modulation for A/D Conversion in Radio Receivers

[3] A cascaded continuous-time ΣΔ modulator with 67-dB dynamic range in 10-MHz bandwidth [J].

Breems, LJ ;

Rutten, R ;

Wetzker, G .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (12) :2152-2160

[4] Excess loop delay in continuous-time delta-sigma modulators [J].

Cherry, JA ;

Snelgrove, WM .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 1999, 46 (04) :376-389

[5]

Cicalini A., 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P368, DOI 10.1109/ISSCC.2011.5746357

[6] 10-bit, 3 mW continuous-time Sigma-Delta ADC for UMTS in a 0.12 μm CMOS process [J].

Dörrer, L ;

Kuttner, F ;

Wiesbauer, A ;

Di Giandomenico, A ;

Hartig, T .

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2003, :245-248

[7] CMOS current-steering DAC architectures based on the triple-tail cell [J].

Grasso, Alfio Dario ;

Mirabella, Carmelo Alessandro ;

Pennisi, Salvatore .

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2008, 36 (03) :233-246

[8]

Lu I. S.-C, 2011, 2011 IEEE International Solid-State Circuits Conference (ISSCC 2011), P364, DOI 10.1109/ISSCC.2011.5746355

[9] THE SOFTWARE RADIO ARCHITECTURE [J].

MITOLA, J .

IEEE COMMUNICATIONS MAGAZINE, 1995, 33 (05) :26-38

[10]

Norsworthy StevenR., 1997, Delta-Sigma Data Converters: Theory, Design, and Simulation

← 1 2 →