A parallel scheme for implementing multialphabet arithmetic coding in high-speed programmable hardware

被引：1

作者：

Mahapatra, S ^{[1
]}

Singh, K ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect & Elect Commun Engn, Kharagpur 721302, W Bengal, India

来源：

ITCC 2005: International Conference on Information Technology: Coding and Computing, Vol 1 | 2005年

关键词：

lossless data compression; multialphabet arithmetic coding; modelling; code interval; pipelined implementation; compression efficiency; LOSSLESS DATA-COMPRESSION;

D O I：

10.1109/ITCC.2005.24

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, a scheme is proposed for parallel-pipelined implementation of the multialphabet arithmetic-coding algorithm used in lossless data compression. Using this scheme, it is possible to parallelize both the encoding and decoding operations used respectively in data compression and decompression. The compression performance of the proposed implementation for both order 0 and order 1 models have been evaluated and compared with existing sequential implementations in terms of compression ratios as well as the execution time using the Canterbury Corpus benchmark set of files. The proposed scheme also facilitates hardware realisation of the respective modules and hence is suitable for integration into embedded microprocessor systems, an important area where lossless data compression is applied.

引用

页码：79 / 84

页数：6

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