Impact of layout, interconnects and variability on CMOS technology roadmap

被引：6

作者：

Boeuf, Frederic ^{[1
]}

Sellier, Manuel ^{[1
]}

Farcy, Alexis ^{[1
]}

Skotnicki, Thomas ^{[1
]}

机构：

[1] STMicroelectronics, 850 Rue Jean Monnet, F-38920 Crolles, France

来源：

2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年

关键词：

D O I：

10.1109/VLSIT.2007.4339712

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, using the new generation of MASTAR software we discuss the CMOS logic roadmap in terms of circuit performance, power dissipation and variability, such as loaded ring-oscillator delay as well as through 6T-SRAM functionality. It is shown that these criteria will have to be taken into account in addition to the traditional 17%/year delay improvement to construct a new industrially viable roadmap.

引用

页码：24 / +

页数：2