Enabling Pre-Assembly Process of 3D Wafers with High Topography at the Backside

被引：0

作者：

Podpod, A. ^{[1
]}

Demeurisse, C. ^{[1
]}

Inoue, F. ^{[1
]}

Duval, F. ^{[1
]}

Visker, J. ^{[1
]}

De Vos, J. ^{[1
]}

Rebibis, K. ^{[1
]}

Miller, R. A. ^{[1
]}

Beyer, G. ^{[1
]}

Beyne, E. ^{[1
]}

机构：

[1] Interuniv Microelect Ctr IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

来源：

2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC) | 2015年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In a specific 3D die to die stacking scenario using a Si interposer technology for high band width interconnect applications', wherein dies including the Silicon interposer were stacked first before placing it onto the substrate, posts a challenge on pre-assembly processes. This paper presents what and which areas the challenges are and reports on the solution found that enabled the pre-assembly processes for 3D wafers with high topography at the backside (Si interposer): a UV dicing tape that can handle the complexities at hand.

引用

页数：5