A High-Performance Low-Power Barrett Modular Multiplier for Cryptosystems

被引：6

作者：

Zhang, Bo ^{[1
]}

Cheng, Zeming ^{[1
]}

Pedram, Massoud ^{[1
]}

机构：

[1] Univ Southern Calif, Ming Hsieh Dept Elect & Comp Engn, Los Angeles, CA 90007 USA

来源：

2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) | 2021年

关键词：

Cryptosystem; large integer arithmetic; Barrett modular multiplication; ARCHITECTURE;

D O I：

10.1109/ISLPED52811.2021.9502490

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a fast architecture for Barrett modular multiplication. By replacing the integer multiplications in each iteration with carry-save compressions and using Booth coding plus operation rescheduling to increase parallelism, we eliminate costly multiplications while concurrently avoiding large-bitwidth additions. Our detailed error analysis proves that intermediate results are always less than twice the modulus. Experimental results show that the removal of multiplication eliminates the need for any DSPs. Even not accounting for this key benefit, compared to the best of prior art results, the proposed design results in 46.8% latency reduction with a similar area.

引用

页数：6

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