A High-Performance Low-Power Barrett Modular Multiplier for Cryptosystems

被引：6

作者：

Zhang, Bo ^{[1
]}

Cheng, Zeming ^{[1
]}

Pedram, Massoud ^{[1
]}

机构：

[1] Univ Southern Calif, Ming Hsieh Dept Elect & Comp Engn, Los Angeles, CA 90007 USA

来源：

2021 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED) | 2021年

关键词：

Cryptosystem; large integer arithmetic; Barrett modular multiplication; ARCHITECTURE;

D O I：

10.1109/ISLPED52811.2021.9502490

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a fast architecture for Barrett modular multiplication. By replacing the integer multiplications in each iteration with carry-save compressions and using Booth coding plus operation rescheduling to increase parallelism, we eliminate costly multiplications while concurrently avoiding large-bitwidth additions. Our detailed error analysis proves that intermediate results are always less than twice the modulus. Experimental results show that the removal of multiplication eliminates the need for any DSPs. Even not accounting for this key benefit, compared to the best of prior art results, the proposed design results in 46.8% latency reduction with a similar area.

引用

页数：6

共 44 条

[21] A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree [J].

Fahim, Farah ;

Joshi, Siddhartha ;

Ogrenci-Memik, Seda ;

Mohseni, Hooman .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (02) :576-584

[22] VLSI Implementation of Low Power High Speed ECC Processor Using Versatile Bit Serial Multiplier [J].

Srinivasan, M. ;

Tamilselvan, G. M. .

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2017, 26 (07)

[23] Low-Power High-Accuracy VCO-Based Comparator for Sensor Interface Applications [J].

Esmaeilzadeh, Mahin ;

Ali, Mohamed ;

Hassan, Ahmad ;

Audet, Yves ;

Sawan, Mohatnad .

2020 18TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS'20), 2020, :254-258

[24] Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems [J].

Nedjah, N. ;

Mourelle, L. M. ;

Santana, M. ;

Raposo, S. .

IET COMPUTERS AND DIGITAL TECHNIQUES, 2012, 6 (05) :290-301

[25] TOWARD A 60-GHz WIRELESS, LOW-POWER, HIGH-THROUGHPUT MEMORY ACCESS SYSTEM [J].

Guidotti, Daniel ;

Chowdhury, Arshad ;

Chien, Hung-Chang ;

Fan, Shu-Hao ;

Chang, Gee-Kung .

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2009, 51 (12) :2969-2973

[26] A low-cost high-speed radix-4 Montgomery modular multiplier without carry-propagate format conversion [J].

Kuang, Shiann-Rong ;

Wang, Chun-Yi ;

Chen, Yen-Jui .

ENGINEERING SCIENCE AND TECHNOLOGY-AN INTERNATIONAL JOURNAL-JESTECH, 2024, 54

[27] High-performance SoC-based implementation of modular exponentiation using evolutionary addition chains for efficient cryptography [J].

Nedjah, Nadia ;

Mourelle, Luiza de Macedo .

APPLIED SOFT COMPUTING, 2011, 11 (07) :4302-4311

[28] RSD-based high-performance radix-4 Montgomery Modular Multiplication for Elliptic Curve Cryptography [J].

Zhao, Shilei ;

Zheng, Jiwen ;

Shao, Yutong ;

Huang, Hai ;

Liu, Zhiwei ;

Yu, Bin ;

Zhang, Ziyue .

MICROELECTRONICS JOURNAL, 2024, 153

[29] VLSI Implementation of Low-Power and High-SFDR Digital Frequency Synthesizer for Underwater Instruments and Network Systems [J].

Juang, Ying-Shen ;

Sung, Tze-Yun ;

Hsin, Hsi-Chin .

ADVANCED MATERIALS: PHYSICS, MECHANICS AND APPLICATIONS, 2014, 152 :289-304

[30] Low-power and high-linearity SiGe HBT low-noise amplifier using IM3 cancellation technique [J].

Lee, Chie-In ;

Lin, Wei-Cheng ;

Lin, Ji-Min .

MICROELECTRONIC ENGINEERING, 2012, 91 :59-63

← 1 2 3 4 5 →