A 5 Gbps 0.13 μm CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

This paper presents a pilot-based clock and data recovery (CDR) technique for highspeed serial link applications where a low-amplitude clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection-locked oscillator and is used to drive the receiver front-end samplers. The performance of the CDR technique is demonstrated using a 5 Gbps differential receiver fabricated in a 0.13 mu m IBM CMOS technology. The clock and data recovery circuit implementation has an area of 0.171 mm(2) and consumes 11.75 mA from a 1.5 V supply voltage at 5 Gbps. The recovered clock peak-to-peak and rms jitter at 5 Gbps are less than 10 ps (5% UI) and 1.6 ps (0.8% UI), respectively with an effective CDR loop bandwidth of approximately 28 MHz at a bit-error rate (BER) of 10(-12). The proposed technique simplifies the CDR design and provides data and intersymbol interference (ISI) independent performance with a small approximate to 5% pilot voltage overhead to the transmitted data signal.