Effects of gate-to-body tunneling current on PD/SOI CMOS latches

被引：0

作者：

Chuang, CT ^{[1
]}

Puri, R ^{[1
]}

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a detailed study on the effect of gate-to-body tunneling current on PD/SOI CMOS latches. The physical mechanism and its impact on the initial quiescent states and performance of the latches are analyzed. It is shown that the effect on latch setup time is particularly significant due to the compounding effect of the master-slave configuration.

引用

页码：291 / 294

页数：4

共 6 条

[1]

Chuang CT, 2002, 2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, P121, DOI 10.1109/SOI.2002.1044444

[2]

CHUANG CT, 2001, 2001 INT C SOL STAT, P262

[3] Controlling floating-body effects for 0.13μm and 0.10μm SOICMOS [J].

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Shahidi, G .

INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :231-234

[4]

FUNG SKH, 2000, P IEEE INT SOI C, P122

[5]

LEEWC, 2000, P VLSI TECHN, P198

[6]

Weste N.H.E., 1988, PRINCIPLES CMOS VLSI

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