Improved assertion lifetime via assertion-based testing methodology

Assertions-based verification (ABV) has been widely used in digital design validation. Assertions are HDL-syntaxed representation of design specification and used as a functional error detection mechanism. During the process of designing with HDLs, assertions are imported which could fire in case of violation during testbench run. Although these assertions are mostly used during simulation and for verifying the functional correctness of the design, but as they illustrate the specifications of a design, it is likely that their lifetime could be extended by embedding them in the chip to detect low level faults like stuck-at faults. In this paper, we introduce a new automatable assertion-based on-line testing methodology. Experimental results show that the synthesis of assertions into a chip, and then using them for online testing, can provide an acceptable coverage for stuck-at faults.