Low noise active loop filter for radar PLL applications

被引：0

作者：

Donno, Andrea ^{[1
,2
]}

D'Amico, Stefano ^{[1
,2
]}

Nonis, Roberto ^{[3
]}

Thurner, Peter ^{[3
]}

机构：

[1] Thetis Microelect Srls, Lecce, Italy

[2] Univ Salento, Dept Innovat Engn, Lecce, Italy

[3] Infineon Technol Austria AG, Villach, Austria

来源：

2018 INTERNATIONAL CONFERENCE ON IC DESIGN AND TECHNOLOGY (ICICDT 2018) | 2018年

关键词：

CMOS analog integrated circuits; operational amplifier; active loop filter; PLL; radar; noise;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a simple structure for a low noise active loop filter, designed in 28nm CMOS process. Design strategies are used for minimizing both thermal and flicker noise at critical frequencies around 1MHz for radar PLL applications. Results show an input referred noise of 2. 81nV/Viz @1MHz for the op-amp of the loop filter, with nominal conditions and 1.8V power supply, occupying an area of 0.039mm(2).

引用

页码：77 / 80

页数：4

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