DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations

被引：0

作者：

Lin, Tung-Liang ^{[1
]}

Chen, Sao-Jie ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei, Taiwan

来源：

2020 IEEE 33RD INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC) | 2020年

关键词：

Design Dependent Critical-Path Monitor (DDCPM); System Control and Management Interface (SCMI); DYNAMIC VOLTAGE;

D O I：

10.1109/SOCC49529.2020.9524768

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel scheme, spatially-correlated Design Dependent Critical-Path Monitor (DDCPM), is proposed, which can provide valuable references in deriving application-specific, process- and temperature-aware DVFS for aggressive power saving during runtime. Such DDCPM utilizes its unique spatial correlation feature and real-time sampling techniques to precisely sense the unexpected behavior introduced by over-scaled voltage under the operating conditions with random and mutually dependent Process-Voltage-Temperature (PVT) variations in each individual chip. Our experimental results obtained in two IPs implemented in TSMC 28 nm process node respectively show average step-wise 7.80% and 8.19% power could be reduced at a smaller granular level of voltage scaling, which corresponding maximum power reductions, 55.6% and 57.5% in Typical Corner could be finally achieved.

引用

页码：141 / 146

页数：6

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