Enabling 10μm Pitch Hybrid Cu-Cu IC Stacking with Through Silicon Vias

被引：11

作者：

Huyghebaert, Cedric ^{[1
]}

Van Olmen, Jan ^{[1
]}

Chukwudi, Okoro ^{[1
]}

Coenen, Jens ^{[1
]}

Jourdain, Anne ^{[1
]}

Van Cauwenberghe, Marc ^{[1
]}

Agarwahl, Rahul ^{[1
]}

Phommahaxay, Alain ^{[1
]}

Stucchi, Michele ^{[1
]}

Soussan, Philippe ^{[1
]}

机构：

[1] IMEC, B-3001 Louvain, Belgium

来源：

2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2010年

关键词：

D O I：

10.1109/ECTC.2010.5490836

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Recently imec demonstrated for the first time 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV) on 200mm wafers [1]. The top tier dies are thinned down to 25 mu m and bonded to the landing wafer by Cu-Cu thermo-compression [2]. Nevertheless, the path towards high volume manufacturing remains to be established. In this paper, we report about fundamental integration issues and discuss possible solutions for further process optimization. The implementation of the proposed solution substantially increased the electrical yield of Cu-Cu joining.

引用

页码：1083 / 1087

页数：5