SiC MOSFET switching - Lower losses without increased EMI - A technique to evaluate and achieve this goal

With increasing switching speed of new power semiconductors like the SiC MOSFET, special attention has to be paid on the electromagnetic interference and its limitations. In this work, an evaluation criterion is developed as an optimisation tool for maximum exploitation of conducted electromagnetic interference limit by optimizing the switching process of a SiC MOSFET. The switching losses of power semiconductors can be reduced by increasing their switching speed. Unfortunately, at the same time, the electromagnetic interference will increase due to higher voltage and current slopes and higher switching oscillations. The electromagnetic interference caused by the switching process can be reduced by decreasing the switching speed. This also reduces the switching oscillation but inevitably increases the switching losses. The electromagnetic interference criterion developed in this paper will help to identify the proper switching speed for minimum losses under compliance with switching process related electromagnetic interference. It can be used to evaluate the benefit of more advanced gate control methods that allow increasing the switching speed without increasing the switching oscillation amplitude. The proposed method will not replace the final electromagnetic interference testing, but it will help determine the proper gate control method for lowest possible switching losses without violating the electromagnetic interference restrictions in an early development state. Measurements show that the switching losses can be reduced by 75% with a proper gate control method, where the proposed method assures the compliance with the electromagnetic interference limit.