COST-EFFICIENT DESIGN AND FIXED-POINT ANALYSIS OF IFFT/FFT PROCESSOR CHIP FOR OFDM SYSTEMS

In this paper, a cost-efficient multiplierless IFFT/FFT processor with its fixed-point error analysis is presented. The IFFT/FFT processor employs the radix-2/48 algorithm, and a proposed classification of twiddle factors (TW) and hardware sharing are used to minimize the nonzero bits of the shift-and-adds operations. After the appropriate wordlengths (WL) of the TWs and teh IFFT/FFT processor input are chosen by the proposed fixed-point quantization noise analysis, a hardware-like fixed-point simulation model of the IFFT/FFT processor is used to develop the Verilog RTL code. The proposed IFFT/FFT processor can achieve packet error rate (PER) less than 0.1 for the test vehicle IEEE 802.11a single-input-single-output (SISO)-OFDM system and slight symbol error rate *SER) loss for the IEEE 802.11n multi-input-multi-output (MIMO)-OFDM system. The core area of the one processor chip is 0.57umx0.565um with 0.18um CMOS process. Besides, the power consumption is 7.74 mW with 1.8 V supply voltage and 40 Mhz system clock.