Simulation of vertical hall sensor in high-voltage CMOS technology

被引：0

作者：

Jovanovic, E ^{[1
]}

Pantic, D ^{[1
]}

机构：

[1] Univ Nish, Nish, Serbia Monteneg, Yugoslavia

来源：

TELSIKS 2003: 6TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS IN MODERN SATELLITE, CABLE AND BROADCASTING SERVICE, VOLS 1 AND 2, PROCEEDINGS OF PAPERS | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we present the vertical Hall magnetic sensor using parameters from conventional high-voltage 0.8 mum CMOS technology. Based on process and device simulations with ISE TCAD system, we demonstrate that sensor characteristic are comparable with those in the magnetic sensors fabricated by specialized non-standard sensor technologies. This was achieved by applying an unconventional doping reduction method. It is demonstrated that deliberate violation of design rules can increase sensitivity without negative influences on the other device characteristics.

引用

页码：811 / 814

页数：4